Typical on-chip and inter-chip electrical interconnections are achieved using copper wires. Several problems result from the physical characteristics of electrical interconnections, including, for example, propagation delay, bandwidth limitations, and power requirements. Resistance and capacitance variations in the electrical interconnection wires create design concerns, such as circuit matching, mutual interference, and crosstalk issues. Electrical interconnections are also limited in their capability to provide point-to-multipoint connections. Optical interconnections have been suggested for use in place of some electrical interconnections to increase bandwidth, reduce parasitic resistance and capacitance, and minimize crosstalk, for example. However, optical interconnections add to manufacturing costs and increases design complexity.
The existing Cisco Catalyst 6500 Crossbar Switching Fabric, such as employed in the Cisco Catalyst 6509 and 6513, is an example of the current art. Eighteen individual fabric channels are apportioned across line card slots in a chassis. This arrangement provides a maximum of two fabric channel connections per line card. Each fabric channel is currently clocked up to 50 Gbps (i.e. 8×6.25 Gbps) full duplex. The maximum data rate out of the line card is 100 Gbps, and the data rate into the line card is 100 Gbps. The total dedicated rate provided is 18×50=900 Gbps. For full duplex operation, this equates to 900 Gpbs×2=1.8 Tbps.
Next generation switching requirements are expected to increase and will be around 3.6 Tbps, or so, with shared bus switching requirements around 1.8 Tbps. For a 50 Gbps link between two line cards, two 50 Gbps links into the switch fabric card are required. Data packets exchanged between the line cards must be routed through a switch Application Specific Integrated Circuit (ASIC). The switch ASIC contains a routing table for routing the data packets between the transmitting and receiving line cards. The use of a switch ASIC requires two links to route packets from the transmitting line card to the receiving line card—one link from the transmitting card to the switch ASIC and a second link from the switch ASIC to the receiving line card. As a result, compared to a direct connection between line cards, twice the power is required and twice the delay is added. The use of a switch ASIC requires increased complexity and additional routing. Combined with the electrical interconnection limitations, it will be difficult to provide the expected future switching requirements.